This invention relates to a semiconductor device having a structure suitable for a CMP (chemical mechanical polishing) process.
The CMP process is a technique frequently used for planarizing the surfaces of an insulating film and conductive film on a semiconductor substrate or filling a conductive film only in trenches or grooves.
Particularly, as the technique for planarizing the insulating film on the semiconductor substrate, the CMP process capable of realizing the flat surface with high precision becomes dominant instead of the planarization technique such as the high-temperature reflow technique and resist etchback technique according to the requirement of lowering of the process temperature due to miniaturization of recent semiconductor elements and a reduction in the focusing margin of photolithography.
When the CMP process is used in the semiconductor manufacturing process, a variation in the planarization of the global area occurring in the entire wafer surface after the end of the CMP process and a variation in the planarization of local areas occurring in a plurality of chip regions in the plane of the wafer are important factors.
In the CMP process, the latter variation in the planarization of the local areas is extremely small and the CMP process is excellent for planarization of the local areas.
However, the CMP process is not always excellent for planarization of the global area, and in the prior art, in order to improve the variation in the planarization of the global area, various devices are made on the CMP device side.
FIGS. 1 and 2 show the schematic structure of a conventional CMP device.
A platen (surface plate) 11 takes a disk-like form and has a rotating shaft. A polishing pad 12 is mounted on the platen 11. The polishing pad 12 is formed of soft non-woven fabric or hard resin.
A film of slurry (which is a solvent containing polishing particles) 13 is formed on the surface of the polishing pad 12.
A wafer carrier 14 holds a wafer 15 by use of a vacuum chuck, for example. The wafer carrier 14 presses the wafer 15 against the polishing pad 12 with a preset pressure so as to permit the slurry 13 to be held between the surface of the polishing pad 12 and the wafer 15.
Also, the wafer carrier 14 has a rotating shaft. The rotating direction a of the platen 11 and the rotating direction b of the wafer carrier are generally set in the same direction in order to reduce a variation in the planarization of the global area.
It is also possible to rotate the wafer carrier 14 in the direction b, and at the same time, revolve the wafer carrier 14 around the rotating shaft of the platen 11 in a direction c while the platen 11 is kept fixed.
In the CMP device of the above structure, the material of the polishing pad 12 gives influence on the flatness of the global area. That is, the flatness of the global area is better in the case of the polishing pad of resin than in the case of the polishing pad of non-woven fabric.
However, if the hard polishing pad which is formed of resin, for example, is used, the following problem occurs.
As shown in FIG. 3, an extremely heavy load caused by the elastic stress of the hard polishing pad 12 is applied to an area extending along the edge portion of the wafer 15, that is, an area inwardly extending from the edge of the wafer 15 by approx. 10 mm maximum.
As a result, the polishing rate for the above area becomes excessively high and cannot be controlled, and the polishing amount in the edge portion of the wafer becomes extremely large in comparison with that in the central portion of the wafer so that a so-called "wafer edge over-polishing" phenomenon in which the edge portion of the wafer 15 is excessively polished occurs.
Generally, beveling is made on the edge portion of the wafer 15, the beveling is made on the order of several .mu.m and is different from the wafer edge over-polishing occurring on the order of several mm. In the following description, the beveling is omitted in order to prevent confusion of the beveling with the wafer edge over-polishing occurring in the CMP process.
The chip region (element region) in the wafer is generally formed in an area which lies on the inner side separated from the edge of the wafer by at least several mm (for example, at least approx. 2 mm).
Therefore, the wafer edge over-polishing occurring in the CMP process gives various influences on the semiconductor manufacturing process.
FIGS. 4 to 7 show one example of the influences given by the wafer edge over-polishing.
First, as shown in FIG. 4, an insulating film (silicon oxide film) 22 is formed on a wafer (silicon substrate) 21 and a plurality of wirings 23 are formed on the insulating film 22. The plurality of wirings 23 are covered with an insulating film (BPSG film, TEOS film or the like) 24. The surface of the insulating film 24 is made irregular depending on the convex and concave portions of the underlying wirings.
After this, when the insulating film 24 is polished to a portion indicated by broken lines by the CMP process, the surface of the insulating film 24 in the central portion of the wafer 21 is made flat as shown in FIG. 5, but a portion of the insulating film 24 in the edge portion of the wafer 21 is excessively polished and thus the wafer edge over-polishing occurs.
As described before, the wafer edge over-polishing occurs in an area which lies at a maximum distance of approx. 10 mm from the edge E of the wafer 21 and reaches the chip region (element region) X.
Further, as shown in FIG. 6, an insulating film 25 is formed on the insulating film 24 and a conductive film 26' is formed on the insulating film 25. After this, a resist pattern 27' is formed on the conductive film 26' by the photolithography process.
In recent years, the size of the wiring pattern is reduced according to miniaturization of elements and the focusing margin of the photolithography is reduced. Therefore, if the wafer edge over-polishing occurs, the precision of processing of the resist pattern 27' near the wafer edge is lowered.
After this, the conductive film 26' is etched with the resist pattern 27' used as a mask by anisotropic etching.
As a result, as shown in FIG. 7, a plurality of wirings 26 are formed on the insulating film 25. However, the thickness of the insulating film 24 near the wafer edge is smaller than the thickness of the insulating film 24 in the central portion of the wafer 21. A difference in the film thickness of the insulating film 24 changes the capacitive coupling between the upper and lower wirings and may cause noises and cause timing delay in signal transmission.
In addition to the above-described problem, it is known that the wafer edge over-polishing causes dusts in the semiconductor manufacturing process, and in the worst case, the pattern of the wafer edge portion is damaged.
Further, the wafer edge over-polishing also occurs when a film is filled only in trenches or grooves by use of the CMP process, for example, when the element isolation method by STI (Shallow Trench Isolation) is applied or when the wiring pattern is formed by the damascene method.
FIGS. 8 and 9 illustrate the wafer edge over-polishing occurring when the element isolation method by STI is applied.
First, as shown in FIG. 8, an oxide film 27 and polysilicon film 28 are formed on a wafer (silicon substrate) 21. A plurality of trenches 29 are formed in the wafer 21, oxide film 27 and polysilicon film 28. An insulating film 30 for completely filling all of the trenches 29 is formed on the polysilicon film 28.
After this, as shown in FIG. 9, the insulating film 30 is polished by the CMP process and the insulating film 30 is left behind only in the trenches 29. At this time, the polishing rate of the edge portion of the wafer 21 becomes extremely higher than the polishing rate of the central portion of the wafer 21 and the wafer edge over-polishing occurs.
The polysilicon film 28 is used as an etching stopper in the CMP process, but since it is not preferable that the position of the surface of the wafer 21 will be greatly deviated from the highest position of the trench 29, the polysilicon film 28 cannot be made excessively thick. Therefore, the wafer edge over-polishing occurs and the edge portion of the wafer 21 is cut out.
FIG. 10 shows an example of a conventional method for improving the CMP device to prevent occurrence of the wafer edge over-polishing phenomenon in the wafer edge.
The feature of the CMP device is that a guide ring 16 is mounted on a wafer carrier 14. The guide ring 16 is disposed to surround a wafer 15, and since it has elastic members 17 such as springs, the load applied to the edge portion of the wafer 15 can be alleviated.
That is, since the CMP device having the guide ring 16 can set the polishing rate of the central portion of the wafer 15 substantially equal to the polishing rate of the edge portion of the wafer 15 in comparison with a CMP device having no guide ring, occurrence of the wafer edge over-polishing can be suppressed.
However, in the above CMP device, it is difficult to control the load applied to the wafer 15 in order to effectively prevent occurrence of the wafer edge over-polishing, and since the guide ring 16 is a consumable part which tends to be polished, it takes a lot of labor for the replacement thereof and the cost is increased.
Thus, conventionally, when the CMP process is effected, the wafer edge over-polishing phenomenon that the wafer edge portion is excessively polished in comparison with the central portion of the wafer occurs, various problems are caused by the phenomenon and the manufacturing yield will be lowered.
Further, means for preventing occurrence of the phenomenon on the CMP device side is studied, but the means cannot attain a preferable effect since it is difficult to control the load applied to the wafer and it raises the cost.